The present invention relates generally to memory circuits, and more particularly pertains to a system and method for increasing the speed of semiconductor memories and memory arrays.
Technological advances have resulted in a continuous increase in the density of semiconductor memory chips, e.g. DRAM, SRAM, Flash, NVRAM, FRAM, etc. For example, improvements on yield control, integration schemes and scaling of the devices have significantly reduced the cost per bit of these memory chips over the years. However, the speed gap between the speed of the memory and the speed of the microprocessor has constantly become wider. Several techniques to enhance memory speed have been proposed recently, such as using an embedded design with a wide data bandwidth, or a special high-speed memory Rambus-like interface protocol. Nevertheless, the speed of memory can hardly keep up with the ever-increasing demands of microprocessors.
It would be highly desirable to provide a method for increasing the speed of memories and memory arrays by reducing the random cycle time thereof.
It is an object of the present invention to provide a system and method for increasing the speed of memories of any type such as semiconductor memories, magnetic memories and optical memories, and is particularly applicable to high speed semiconductor memories and memory arrays, such as high speed DRAM caches.
It is a further object of the subject invention to provide a system and method for increasing the speed of memory arrays, particularly by decreasing the random cycle time thereof.
As mentioned earlier, the packing densities of memory are generally quite high. The cell size of DRAM (dynamic random access memory) has decreased to less than 0.2 um2 by using a deep-trench or high-K material with a stacked structure as the memory capacitor.
The present invention trades memory density (or area) for memory speed (or cycle time). The subject invention duplicates a memory with an array of n2 memories in order to reduce the random cycle time thereof by 1/n. For example, if an existing memory cycle time is 6 ns, in order to achieve a 3 ns (or n=2) cycle time, an array of 4 memories is used, or in order to achieve a 1.5 ns (or n=4) cycle time, an array of 16 memories is used, or in order to achieve a 1 ns cycle time (or n=6), then an array of 36 memories is used, with n being extendable to any number depending upon the desired speed and application.
Advantageously, the system and method of the present invention can increase the speed or cycle time of almost any kind of memory including semiconductor, magnetic and optical memories, and read-only and write-only memories.